1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to an EEPROM (Electrically Erasable Programmable ROM) having memory cells of NAND structure in which data readout speed is improved.
2. Description of the Prior Art
An example of the configuration of a memory cell of the NAND type EEPROM is shown in FIG. 8. Source region 2 and drain region 3 which are n-type impurity regions are formed in the surface of p-type semiconductor substrate 1, and channel region 4 is formed between the drain 3 and the source 2. Floating gate (FG) 6 is formed above the channel 4. Gate insulation film 5 is formed between the channel 4 and the floating gate 6. Furthermore, control gate (CG) 7 is formed above the floating gate 6. An insulating film is formed between the floating gate 6 and the control gate 7. The gate insulating film 5 has a thickness sufficient to allow an electron tunnel effect to occur between the channel region 4 and the floating gate 6.
In such a memory cell, data write operation will be carried out as follows. One of binary data is written by emitting electrons from the floating gate 6 to the semiconductor substrate 1. In order to emit electrons from the floating gate, the control gate 7 is set to zero volts and the substrate 1 is set to a high voltage. Electrons are emitted from the floating gate 6 into the substrate 1 through the gate insulating film 5 by using the tunnel effect. The other of binary data is written by injecting electrons into the floating gate 6 from the substrate 1. In order to inject electrons into the floating gate 6, the substrate 1, the source 2 and the drain 3 are set to zero volts, and the control gate 7 is set to a high voltage. Consequently, electrons are injected into the floating gate 6.
A portion of a semiconductor memory device constructed as an integrated circuit in which a plurality of memory cells as mentioned above are connected in a matrix form is shown in FIG. 9.
This semiconductor memory device includes memory cell array in which memory cell blocks are arranged in a matrix form. Each of the memory cell blocks includes a select transistor(S1), memory cells(11-1n) and a transistor(P1). Respective memory cell blocks are selectively connected to column lines (bit lines) BL1-BL2 by select transistors S1, S2 provided between the column lines and the respective memory cells. Moreover, transistors P1, P2 for providing a reference potential to the memory cell blocks are also connected between the respective memory cells and a reference potential. The gates of select transistors S1, S2 in the same row are commonly connected to a select line. Select signal SL is applied to the select line. Further, the gates of the transistors P1, P2 are also commonly connected and are controlled by signal .phi.. In addition, the gates of the memory cells in the same rows are commonly connected to one of the row lines (word lines) WL1-WLn.
The operation in the configuration shown in FIG. 9 will now be described with reference to FIGS. 10A-10F which is the voltage waveforms of respective nodes.
In the case of programming data into a memory cell, all row lines WL1-WLn connected to control gates 7 are set to zero volts and the substrate 1 is set to a high voltage to thereby discharge electrons from the floating gates of all memory cells into the substrate. Then, a select signal of a high potential is applied to the gate of the select transistor of the memory cell block including the memory cell into which data is to be written. At the same time, signal .phi. is set zero volts to allow transistors P1, P2 to be turned OFF, thus to separate the memory cell from the reference potential.
Further, in the case of injecting electrons into the floating gate of the memory cell, the corresponding row line WL is set to high potential V1 and the corresponding column line BL is set to zero volts. At this time, a potential difference between the floating gate and the substrate becomes a sufficient value to allow an electron tunnel effect to occur between the floating gate and the substrate. Thus, electrons are injected from the substrate into the floating gate.
On the other hand, the row line WL which is not selected is set to a potential of V2 lower than the potential V1. At this time, even if a potential of the column line is zero volts, since the potential V2 is lower, a potential difference between the floating gate and the substrate does not become a sufficient value such that the tunnel effect occurs, so no electron is injected into the floating gate of the memory cell which is not selected. When electrons are not injected into the floating gate of the selected memory cell which is connected to the selected row line, a potential of the column line BL is set to a potential of V3. A potential difference between the floating gate of the memory cell and the substrate (the channel region of the memory cell) does not become a sufficient value to allow the electron tunnel effect to occur between the floating gate and the substrate, even if the potential of the row line WL is the high potential V1. Consequently, no electron is injected into the floating gate of the memory cell when the potential V3 is applied to the selected column line. In FIGS. 10A-10F, the row lines WL1 and WLn are the potentials V2 and V1 respectively at time period T1, electrons are injected into the floating gate of memory cell 2n since the column line BL2 is zero volts, but no electron is injected into the floating gate of memory cell 1n since the column line BL1 is the potential V3. Similarly, the row lines WL1 and WLn are the potentials V1 and V2 respectively at time period T2, electrons are injected into the floating gate of memory cell 11 since the column line BL1 is zero volts, but no electron is injected into the floating gate of memory cell 21 since the column line BL2 is the potential V3.
As stated above, electrons are emitted from the floating gates of all memory cells first. Consequently, the threshold voltages of the memory cells change to a negative value. One of binary data is programmed into the memory cells by emitting electrons from the floating gate. And then, electrons are selectively injected into the floating gate of the memory cell. Consequently, the threshold voltage of the memory cell into which electrons are injected changes to a positive value. The other data of the binary data is selectively programmed by injecting electrons into the floating gate.
When the data stored in the memory cell is read, a selected row line is set to a logic "0" level, e.g., 0 volts, and non-selected row lines are set to a logic "1" level, e.g., 5 volts. Memory cells connected to the non-selected row lines are turned ON even if electrons are injected into the floating gate of the memory cell, because the non-selected row line is a logic "1". However, since the selected row line is 0 volts, the selected memory cell is turned OFF if the threshold voltage of the memory cell is positive, but if the threshold voltage of the selected memory cell is negative, the memory cell is turned ON.
Accordingly, it is possible to detect whether data stored in the memory cell is a logic "1" level or a logic "0" level according to whether the selected memory cell is turned ON or OFF.
With such readout method, since the threshold voltage of the memory cell where electrons are injected into the floating gate must be set so that the memory cell is turned ON when it is in the non-selected state and that memory cell is turned OFF when it is selected, the quantity of electrons injected should be carefully be controlled.
For this reason, the injecting electrons into the memory cell and the reading data from the memory cell for checking the quantity of electrons injected are performed repeatedly, thus to stop injection of electrons when the quantity of electrons injected is equal to a suitable value. However, since electrons are injected through an extremely thin gate insulating film, the threshold voltages of the memory cells after the injection of electrons do not become uniform, and vary according to a certain distribution owing to subtle variations of thickness of the gate insulating film and a manufacturing process. For this reason, quantities of electrons injected into the floating gates in respective memory cells become diverse.
As stated above, generally, the threshold voltage of the memory cell into which electrons are injected varies within a certain range. Accordingly, a difference between a threshold voltage value of the memory cell having the lowest threshold voltage and a threshold voltage value of the memory cell having the highest threshold voltage results in a difference between currents flowing in these memory cells, so readout speed of data from a selected memory cell varies for different memory cells. Since data is detected by a current flowing through non-selected memory cells connected in series, unevenness between threshold voltages of non-selective memory cells results in unevenness between currents flowing in memory cells as it is, and further results in unevenness of data readout speed.
For the purpose of increasing data readout speed, it is desirable that a quantity of current flowing in the memory cell is made larger. However, since the threshold voltage of the memory cell into which electrons are injected must be positive, even if the threshold voltage of the memory cell having the lowest threshold voltage is set to a value slightly higher than zero volts, the value of the threshold voltage of the memory cell having the highest threshold voltage would be a value far higher than zero volts by unevenness of the distribution of threshold voltages of the memory cells. Thus, a current flowing in the memory cell having the highest threshold voltage becomes a small value, so it takes much time for reading out data.
For this reason, there is conventionally proposed a technique. Data are read at a time from all memory cells connected to a selected one row line WL. The data read from the memory cells of one row line are latched in latch circuits. And the data of the latch circuits are sequentially read out. When such technique is employed, it takes much time in readout from the first selected memory cell, but the data from the next memory cells can read in a short time in continuous addresses. Consequently, overall data readout time can be reduced, thus making it possible to read out data at a high speed.
In such a technique, since a current flowing in the memory cell is extremely small, readout of data has been carried out by precharging respective column lines thereafter to detect whether the column line is discharged by the memory cell or remains charged without being discharged. In this case, since the charge path to the column line is lost after the column line is precharged, the column line is rapidly discharged by the memory cell after the precharge of the column line is completed. And it is possible to satisfactorily ensure the low potential level of the column line even if a current flowing in the memory cell is small.
However, since such charge operation has been conventionally carried out so that a charge potential reaches a power supply potential, a current required for charging all column lines has been instantaneously extremely large. For allowing the readout speed to be high, it is necessary to carry out precharge in a short time. For this reason, an instantaneous peak current at the time of carrying out precharge has been extremely large. With the progress of the miniaturization technology of the semiconductor integrated circuit, the spacing between column lines has been become smaller and smaller. As a result, the capacitive coupling between column lines has not been negligible. In the conventional precharging method as described above, there is no charge path after precharge is completed. For this reason, a column line to which a selected memory cell which remains in OFF state is connected is placed in a electrically floating state after precharge is completed. On the other hand, a column line to which a selected memory cell which remains in ON state is connected is discharged by the memory cell in ON state. As a result, a potential of the column line gradually lowers. When a column line to which a memory cell in ON state is connected and a column line to which a memory cell in OFF state is connected so that the column line is in an electrically floating state are adjacent to each other, a potential of the column line to which the memory cell in OFF state is connected drops followed by potential drop of the column line connected to the memory cell in ON state by capacitive coupling between the two column lines. With the progress of miniaturization, the coupling capacitance between column lines increasingly has become large, and the potential drop of a column line in the electrically floating state also increasingly become large. For this reason, the potential of the column line which is precharged drops, so any erroneous operation may take place.